Via and metal line interface capable of reducing the incidence of electro-migration induced voids

ABSTRACT

Embodiments of the invention include a method for forming copper interconnect structure. The method involves providing a substrate having a copper conductive layer formed thereon. An insulating layer having openings is formed on the conductive layer so that the openings expose portions of the underlying conductive layer at the bottom of the openings. A barrier layer is formed on the surface of the substrate. A portion of the barrier layer is removed at the bottom of the opening to expose the underlying conductive layer. A copper plug is formed in the opening such that the bottom of the plug is in contact with the exposed conductive layer. The substrate can be subjected to further processing if desired. The invention also includes a copper interconnect structure having increased resistance to electromigration.

TECHNICAL FIELD

The invention described herein relates generally to semiconductordevices and processing. In particular, the invention relates tosemiconductor devices and processes that incorporating improved via andcopper interconnect structures. And most particularly, the inventionrelates forming an improved interface between a copper interconnect andan associated copper-filled via structure.

BACKGROUND

The semiconductor industry makes wide use of copper conductive lines andinterconnect structures in the construction of semiconductor devices.Copper has proven to be a very useful material for a number of reasons.For example, copper has a lower resistivity than aluminum. As a result,copper circuitry suffers less from resistance-capacitance (RC) delays.This makes copper systems faster.

However, copper has the disadvantage of high diffusivity throughdielectric and silicon materials on which the copper is deposited. Thisis especially problematic when used with so-called low-K dielectricmaterials, which are coming into increasingly common usage. Diffusion ofcopper into insulating layers comprised of low-K dielectric materialscan result in serious problems. Diffusion of copper into low-K materialstypically “poisons” the materials so that semiconductor device failureis common. The industry has adapted to this problem by implementingbarrier layers to prevent the diffusion of copper into the affectedmaterials. Typically, the barrier materials consist of thin layers ofmaterial interposed between copper layers and low-K dielectric layers.

Although such barrier layers are effective at preventing the diffusionof copper materials, such barrier layers come with their own set ofprocess difficulties. One such problem is that barrier layers cancontribute to electromigration induced voiding in copper interconnectstructures. Such voiding is a common source of circuit failure in copperbased semiconductor structures. Such voiding is particularly problematicwhen it occurs in via structures. Research has shown thatelectromagnetic voiding is particularly common at the interface betweenthe copper layer and the barrier layer.

This problem can be illustrated with reference to the schematiccross-section views illustrated in FIG. 1(a) and FIG. 1(b). In FIG.1(a), a conventional semiconductor substrate 100 is depicted. A wafersurface 102 is depicted with a metal interconnect line 104 formedtherein. Such wafers 102 are commonly formed of silicon or dopedsilicon. The metal interconnect line 104 is typically formed usingcopper or copper-containing materials (e.g., copper alloys or copperlaminates and the like). An insulating layer 105 comprised ofelectrically insulating material (e.g., SiO₂, low-K dielectrics, andother like materials) is formed over the wafer surface 102. In order tomake electrical connections to overlying layers (not shown) openings 108are formed in the insulating layer 105 to expose the underlying metalinterconnect line 104. Such openings 108 are commonly formed usingdamascene or dual-damascene fabrication processes. A barrier layer 106is commonly formed on the wafer surface 102 covering the insulatinglayer 105 and also covering the bottom and sidewalls of the opening 108.Subsequently, a plug 107 is formed in the opening 108 to form a viastructure. The plug 107 is formed of a copper or copper-containingmaterial constructed using ordinary fabrication techniques known topersons having ordinary skill in the art. The barrier layer 106 preventsdiffusion of the copper from the plug 107 into the insulating layer 103.

An additional feature of such structures are the presence of minutevoids 105 in the interconnect line 104. During the ordinary operation ofintegrated circuit structures containing such copper interconnects,copper atoms migrates within the interconnect lines 104. Additionally,it has been determined that one of the major pathways for such coppermigration is the interface 110 between the interconnect line 104 and thebarrier layer 106. Under certain common operating conditions this coppermigration causes the voids 105 to move. In the depicted embodiment, thevoids 105 move in a direction indicated by the arrow 111. Over time themigrating voids 105 tend to aggregate.

As depicted in FIG. 1(b) the aggregate voids 105′ can become quitesizable. In fact the aggregate voids 105′ can be come so large that theyocclude the conduction pathways in the interconnect lines 104. Also, theaggregate voids 105′ can occlude the connections between certain viasand the interconnect lines. FIG. 1(b) depicts this problem. Theaggregate void 105′ has migrated to the interface between the plug 107and the interconnect line 104. Also, the aggregate void 105′ has grownso large that it destroys the current path between the plug 107 and theinterconnect line 104. Current solutions to this problem require that asecondary via be constructed so that when one via fails a conductionpath can still be achieved through the secondary via. Although suchsolutions work well enough for their intended purpose, improvedsolutions are desirable.

SUMMARY OF THE INVENTION

In accordance with the principles of the present invention, an improvedinterconnection structure and method for its fabrication are disclosed.

In general, the present invention is directed toward methods andstructures that formed interconnect structures having increasedelectromigration lifetimes and a lower incidence of void induced circuitfailures. In one implementation of the invention, vias are formed sothat there is no barrier layer formed at the interface between thebottom of a copper plug and the underlying copper line. As desired, suchstructures can exhibit increased electromigration lifetimes and a lowerincidence of void induced circuit failures.

One embodiment of the invention includes a method for forming a copperinterconnect structure. The method involves providing a substrateconfigured in readiness for conductive via formation. The substrateincludes a conductive layer formed of copper-containing material with aninsulating layer formed thereon. The insulating layer has an openingthat exposes a portion of the underlying conductive layer. A barrierlayer is formed on the insulating layer and on the surfaces of theopening as well as on the exposed portion of the conductive layer. Theportion of the barrier layer at the bottom of the opening is removed toexpose a portion of the underlying conductive layer. A conductive plugis formed with a copper-containing material in the opening such that thebottom of the plug is in contact with the exposed conductive layer.Thus, the interface between the plug and the underlying conductive layeris formed without a barrier layer at the interface.

In a related embodiment, the barrier layer is formed as a non-uniformbarrier layer having a greater thickness on the insulating layer and onthe sidewalls of the opening, whereas the portion of the barrier layerformed on the bottom of the opening is formed having a relativelythinner dimension.

Another embodiment comprises a copper interconnect structure. Thestructure comprises a semiconductor substrate having a conductive layerformed thereon. The conductive layer being formed of copper-containingmaterials. An insulating layer is formed on the conductive layer andincludes openings that expose portions of the underlying conductivelayer at the bottom of the openings. The openings include a layer(s) ofbarrier material formed on the sidewalls of the openings. The barrierlayer(s) is formed of materials that are resistant to copper diffusionto prevent copper from diffusing into the insulating layer. Conductiveplugs comprised of copper-containing material are formed in the openingssuch that the bottom of the plugs are in contact with the underlyingexposed portions of the conductive layer.

Other aspects and advantages of the invention will become apparent fromthe following detailed description and accompanying drawings whichillustrate, by way of example, the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description will be more readily understood inconjunction with the accompanying drawings, in which:

FIGS. 1(a) and 1(b) are simplified schematic cross-section views of aconventional copper interconnect structure illustrating the problem ofvoiding in conventional circuit structures.

FIGS. 2(a)-2(d) are simplified cross-sectional views of a semiconductorsubstrate used to illustrate aspects of a method embodiment used toconstruct an interconnect structure in accordance with the principles ofthe invention.

FIGS. 3(a)-3(d) are simplified cross-sectional views of a semiconductorsubstrate having an interconnect embodiment formed thereon in accordancewith the principles of the invention.

FIGS. 4(a)-4(d) are simplified cross-sectional views of a semiconductorsubstrate illustrating yet another embodiment of an interconnectstructure formed thereon in accordance with the principles of theinvention.

FIG. 5 is a figurative depiction of a semiconductor wafer formed havinginterconnect structures of the type described herein comprising part ofits circuitry in accordance with the principles of the invention.

FIG. 6 is a flow diagram that describes a method embodiment forimplementing a process for constructing a copper interconnect inaccordance with the principles of the present invention.

It is to be understood that in the drawings like reference numeralsdesignate like structural elements. Also, it is understood that thedepictions in the Figures are not necessarily to scale.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention has been particularly shown and described withrespect to certain embodiments and specific features thereof. Theembodiments set forth hereinbelow are to be taken as illustrative ratherthan limiting. It should be readily apparent to those of ordinary skillin the art that various changes and modifications in form and detail maybe made without departing from the spirit and scope of the invention.

In the following detailed description, various method embodiments forforming conducting structures in layers of insulating materials will bedisclosed. In particular, the depicted structures show the formation ofcopper conducting structures that are suitable for interconnectingcopper lines of one layer in a multi-layer semiconductor device to otherunderlying copper lines. The inventors specifically contemplate that theprinciples of the invention are not strictly confined to coppermaterials but that they can also be applied to copper-containingmaterials as well. Moreover, the inventors contemplate that theprinciples of the invention are not limited to just interconnect and viastructures, but that they can also be applied to any interconnectionsbetween conducting structures in a semiconductor substrate.

During ordinary course of operation, the via 107 of FIGS. 1(a) and 1(b)has a high density of copper (Cu) ion flux. The presence of the barrierlayer 106 in region 110 contributes significantly to the formation ofvoids at the metal/via interconnect. An aspect of the present inventionis directed to reducing the incidence of voiding and circuit failure atthe interface between the via and the underlying conducting layer byremoving the barrier layer at the interface.

FIGS. 2(a)-2(d) illustrate one method embodiment used for constructingan improved via/interconnect structure. FIG. 2(a) depicts a suitablesubstrate in readiness for the formation of such an improvedvia/interconnect structure. The substrate 200 typically comprises asemiconductor substrate having a conducting layer 204 formed thereon.Such conducting layers 204 are typically, formed of copper-containingmaterials. One typical example is a conducting layer 204 that iscomprised substantially of copper. However, the inventors point out thatsuch copper containing conducting layers 204 can include, withoutlimitation, copper alloy materials, multi-layer structures containingcopper, as well as other like materials.

An insulating layer 203 is formed on the substrate surface. Theinsulating layer 203 is formed over the conducting layer 204. Theinsulating layer 203 is commonly referred to as an inter-layerdielectric (ILD). Although in many implementations, a barrier materialis formed over the conducting layer 204 such that the ILD 203 lies overthe barrier material. The barrier material is intended to prevent copperdiffusing from the conducting layer 204 into the ILD 203. Forillustration purposes these drawings do not include the aforementionedbarrier material.

In continuation, for many embodiments the ILD 203 is formed of low-Kdielectric materials or other electrically isolating materials. Theprinciples of the present invention find particular utility when appliedto use with low-K dielectric materials. Examples of such materialsinclude spin-on and CVD polymeric materials based on silicon or carbon,or based on combinations of silicon and carbon. Particular low-Kmaterials include, but are not limited to: organic thermoplastic andthermosetting polymers such as polyimides, polyarylethers,benzocyclobutenes, polyphenylquinoxalines, polyquinolines; inorganic andspin-on glass materials such as silsesquioxanes, silicates, andsiloxanes; and, mixtures, or blends, of organic polymers and spin-onglasses. Further, examples of CVD low-K materials include SiCOH orpolymers of parylene and napthalene, copolymers of parylene withpolysiloxanes or teflon, and polymers of polysiloxane. Other ILD 203materials include, but are not limited to, silicon dioxide orcombinations of silicon dioxide and other doped dielectrics (e.g., BPSG,PSG).

Openings 208 are formed in the ILD 203 to expose the underlyingconducting layers. Such openings 208 are typically formed usingmethodologies well known to those having ordinary skill in the art.Suitable techniques include, but are not limited to, damascene and dualdamascene fabrication processes. So far, the structure 200 is formed inaccordance with well-known convention semiconductor fabricationprocesses. The openings expose a portion of the underlying conductinglayer 204.

In many applications, the substrate is now pre-cleaned to remove nativeoxides. In particular, such pre-cleaning is employed to remove a thinlayer of copper oxide from the exposed portion of the underlyingconducting layer 204 at the bottom of the opening. A typical approachfor pre-cleaning involves sputtering the surface with a plasma formedusing argon, hydrogen, or carbon fluoride (CF_(x)) materials. Suchsputtering should be conducted until about 50 Å of oxide are removed.Techniques for achieving such pre-cleaning are known to persons havingordinary skill in the art. At this point a copper diffusion barrierlayer 206 can be formed.

Such a barrier layer 206 is formed on the substrate. In particular, thebarrier layer 206 is formed so that it coats the sidewalls and bottom ofthe opening 208. In the depicted embodiment, the barrier layer 206covers the underlying conducting layer 204 to form a bottom barrierlayer 206 b. The disadvantages of this bottom barrier layer 206 b havealready been discussed. The barrier layer 206 is formed to prevent thediffusion of copper into the ILD 203. Typical barrier materials includetantalum (Ta) or titanium (Ti) based barrier materials (e.g., tantalumnitrides (TaN), tantalum silicon nitrides (TaSiN), or titanium nitrides(TiN)). Additionally, multi-layer barrier layers can be formed. Also,graded layer barrier layers 206 can be used. Such layer can be augmentedwith other layers that incorporate materials like magnesium (Mg),palladium (Pd), chromium (Cr), and molybdenum (Mo), vanadium (V),tungsten (W), or other related materials Alternatively, barrier layers206 comprised of silicon carbide (SiC) and silicon carbon nitride (SiCN)or other like materials can be used. Such barrier layers 206 can beformed using conventional approaches. For example a TaN barrier layer206 can be formed using physical vapor deposition (PVD) or chemicalvapor deposition (CVD) techniques or even atomic layer deposition (ALD).Commonly, such layers are formed in the range of about 5 Å to 400 Åthick with a preferred thickness in the range of in the range of about150-250 Å thick.

One of the difficulties in the present art is that such barrier layers206 can not be formed without forming a thin barrier layer 206 b on thebottom of the opening 208. It is this bottom barrier layer 206 b thatinduces much of the voiding problem. Thus, an advantageous aspect of theinvention concerns removing the bottom portion 206 b of the barrierlayer 206.

Typically, the bottom barrier layer 206 b is removed by anisotropically(directionally) etching the substrate. Such anisotropic etching can beachieved in a number of ways known to those having ordinary skill in theart. For example, plasma etching, reactive ion etching (RIE), or ionmilling can be used. One preferred etch chemistry used to remove thebottom barrier layer 206 b includes etchants chosen from among thecarbon fluoride family of etchants (e.g., C_(x)H_(y)F_(z)). For example,CF₃H and CF₄ are suitable etchants. Additionally, sulfur fluoride(SF_(x)) etchants such as SF₆ are also satisfactory. Moreover, boronchloride etchants (e.g., BCl₃ as well as others) can be used inembodiments of the invention. Additionally, chlorine gases can be usedas etchants in accordance with the principles of the invention. Theseetchants are flowed into a suitable process chamber and then ignited toform an etchant plasma. The substrate is exposed to the etchant plasmauntil the bottom barrier layer 206 b is removed. It is specifically,pointed out that these disclosed etchants encompass a wide range ofsimilar etchants known to persons having ordinary skill in the art thatare suitable for removing the bottom barrier layer 206 b.

Many different tools can be employed to accomplish the many operationsof the disclosed process. FIG. 2(b) illustrates the application of anetchant plasma 207 being directed vertically onto the substrate 200.Particularly, the etchant plasma 207 is directed vertically onto thebottom barrier layer 206 b. One example of a suitable tool is an Endura5500 PVD tool manufactured by Applied Materials, Inc. of Santa Clara,Calif. In one implementation, the following process parameters can beused to anisotropically remove the bottom barrier layer 206 b. Such aprocess operates in a plasma operating at relatively low pressure. Suchplasma is generated at a power in the range of about 200-2000 W and apressure of less than 75 mTorr, preferably less than about 20 mTorr andstill more preferably, operating in the range of about 0.05 mTorr toabout 7 mTorr. Moreover, a relatively high wafer bias, in the range ofabout 50 volts (V) to about 400 volts should be used to effectivelyremove the material of the bottom barrier layer 206 b. One preferredimplementation uses a power of about 200 W at about 7 mTorr with a waferbias of about 50V. Under such conditions a TaN bottom barrier layer 206b of about 150 Å thick can be removed in about 30 s (seconds). Theinventors point out that the aforementioned parameters and specificapplications are given merely as an example that illustrates much widerprinciples of operation.

FIG. 2(c) the intended effect of the previously described anisotropicetching. Such anisotropic etching removes the bottom barrier layer 206b, exposing a portion of the underlying conducting layer 204. Theexposed conducting surface 204 s is now in readiness for copperinterconnect formation.

Referring to FIG. 2(d) a copper-containing material is formed in theopening to create a conductive plug 210. The processes for forming suchcopper-containing plugs 210 are well known. For example, a thin seedlayer of copper material can be formed on the barrier layer 206 in theopening 208. This is followed by the bulk deposition of a much thickercopper layer of copper material.

A suitable method for forming a copper seed layer is disclosed in U.S.Pat. No. 6,037,258 to Liu, et al. entitled “Method of Forming a SmoothCopper Seed Layer for a Copper Damascene Structure”, which is herebyincorporated by reference. In one embodiment, the seed layer 202 can beformed by deposition using PVD techniques. One suitable process employsa PVD machine (e.g., the Endura 5500) at a power in the range of about10-100 kW at a pressure of about 0.05 mTorr to about 5 mTorr. This seedlayer is formed to a thickness of about 50-100 Å.

The bulk copper layer is formed over the copper seed layer. The bulkcopper layer is typically formed using bulk deposition techniques likeelectroplating. One suitable embodiment for forming the bulk copperbarrier layer uses electroplating. An example process employs an AppliedMaterials Electra ECP machine using a copper sulfate solution having aplating current of about 10 A/cm to 100 A/cm. The bulk copper layer 203is plated until the opening 171 is filled.

Other copper deposition techniques can be used as well. The finalstructure should demonstrate good electrical contact between the plug210 and the underlying conducting layer 204 at the interface 211 betweenthe plug 210 and the underlying conducting layer 204. Moreover, there isno barrier layer at the interface 211 between the plug 210 and theunderlying conducting layer 204. Typically, once the plug 210 is formedit is subjected to chemical mechanical planarization (CMP) to form thedepicted structure

The structure depicted in FIG. 2(d) can be subjected to furtherprocessing to create additional layers if desired. For example, anotherbarrier layer (or capping layer) can be formed over the structuredepicted in FIG. 2(d) and another ILD can be formed. Further vias andconducting lines can also be formed. It should be readily appreciated bythose having ordinary skill in the art that other conductive structuresincluding, but not limited to: interconnects, trenches, trenchesoverlying vias, contacts and the like, can be constructed using theprinciples of the present invention.

FIGS. 3(a)-3(d) depict a slightly different embodiment than thatdepicted in FIGS. 2(a)-2(d). FIG. 3(a) depicts a suitable substrate inreadiness for the formation of an improved via/interconnect structure.The substrate 300 is similar to that depicted in FIG. 2(a). Thesubstrate includes a conducting layer 204 formed thereon. Suchconducting layers 204 are typically formed of copper-containingmaterials as described hereinabove with respect to FIGS. 2(a)-2(d). Asabove, an insulating layer 203 is formed on the substrate surface. Theinsulating layer 203 is formed over the conducting layer 204. As above,the insulating layer 203 can be formed of a wide range of electricallyinsulating materials including low-K dielectric materials. Also asabove, openings 308 are formed in the insulating layer 203 usingmethodologies well known to those having ordinary skill in the art. Theopenings expose a portion 304 b of the underlying conducting layer 204.Also as previously disclosed, in many applications, prior to theformation of a barrier layer the substrate can be pre-cleaned to removenative oxides. Such pre-cleaning is conducted as described above.

With reference to FIG. 3(b), a non-uniform layer of barrier layer 306 isformed on the surface of the substrate 300. In particular, thenon-uniform barrier layer 306 is formed on the bottom surface of theopening 306 b (i.e., on the exposed portion of the conducting layer 204)and on the sidewalls 306 s of the opening. In particular, thenon-uniform barrier layer 306 is formed having a greater thickness ontop of the substrate (e.g., on the insulating layer 203, such layer notbeing shown here) than on the bottom surface of the opening 306 b. Also,the layer thickness on the sidewalls 306 s is greater than the thicknessof the bottom surface of the opening 306 b. Heretofore, conventionalprocesses expended great effort to avoid this non-uniformity in barrierlayers. However, the prior art has not contemplated the advantagesobtainable using such a non-uniform barrier layer.

A non-uniform barrier layer 306 can be formed on the substrate using anumber of methodologies known to those having ordinary skill in the art.A few suitable examples are now disclosed. The barrier layer 306 isformed so that the bottom 306 b is thinner than the sidewalls 306 s orthe top surfaces (not shown here). Typical barrier materials includetantalum (Ta) or titanium (Ti) based barrier materials (e.g., tantalumnitrides (TaN), tantalum silicon nitrides (TaSiN), or titanium nitrides(TiN)). Additionally, multi-layer barrier layers can be formed. Also,graded layer barrier layers 306 can be used. Such layer can be augmentedwith other layers that incorporate materials like magnesium (Mg),palladium (Pd), chromium (Cr), and molybdenum (Mo), vanadium (V),tungsten (W), or other related materials Alternatively, barrier layers206 comprised of silicon carbide (SiC) and silicon carbon nitride (SiCN)or other like materials can be used. Such barrier layers 206 can beformed using conventional approaches.

In one preferred embodiment, a tantalum based barrier layer 306 isformed using a uni-directional PVD process. A PVD tool such as an Enduramanufactured by Applied Materials, Inc. of Santa Clara, Calif. can beused to obtain a suitable barrier layer 306. For example, a tantalumbarrier layer 306 can be formed by placing a substrate in a processchamber and then flowing argon (Ar) into the chamber. The Ar is ignitinginto plasma and used to sputter tantalum off a tantalum target. Thesputtered tantalum 350 is directed by a bias voltage onto the substrate.In order to enhance the non-uniform distribution of material onto thesurfaces of the opening 308, the tantalum is directed onto the substrateat a deposition angle θ (which is other than perpendicular to thesurface). Although, many different deposition angles are possible,preferred angles are in the range of about 10 degrees (°) to about 80°.Such deposition angles θ can be achieved by many different approachesknown to persons having ordinary skill in the art. For example, themagnetic fields of the deposition chamber can be adjusted so that adesired deposition angle θ can be achieved. Thus, a unidirectionaldeposition of tantalum (or other selected barrier material) can beaccomplished. To form a barrier layer 306 on all sides of the opening308 the substrate can be rotated which the deposition angle θ remainsconstant. This causes a relatively even axial deposition of tantalum.However, the same process results in a non-uniform distribution ofmaterial occurring such that barrier material at the bottom of theopening (e.g., 306 b) is relatively thinner than the barrier materialformed on the sidewalls (e.g., 306 s). This non-uniform distribution ofbarrier layer thickness is what is meant by a non-uniform barrier layer306. For example, in one implementation, the thickness of the barrierlayer 306 on the surface of the insulating layer 203 (not shown here)can be about 1500 Å thick and a corresponding sidewall 306 s thicknesscan be in the range of about 400-800 Å thick and a corresponding bottomlayer 306 b thickness can be in the range of about 100-200 Å thick.Thus, the bottom can be made very thin while still forming an effectivebarrier layer on the sidewalls 306 s. Such a configuration can beachieved using an Endura PVD tool operating a power range of about1000-24,000 W (target power). As Ar is flowed onto the chamber it isignited into a plasma which sputters a tantalum target. Such processoccurs at a pressure of less than about 20 mTorr, preferably operatingin the range of about 0.5 mTorr to about 5 mTorr. The substrate can belightly biased, in the range of about 50 W to about 500 W to direct thetantalum onto the substrate. As explained, in some embodiments magneticfields can be used to achieve a desired deposition angle for thetantalum. Additionally, N₂ can be flowed into the chamber to form abarrier layer that comprises tantalum nitride material. Many othermaterials can be used and uni-directionally deposited to achieve anon-uniform barrier layer 306 being thinner of the sides and the topthan on the bottom. One preferred implementation deposits a tantalumbarrier layer 306 using a power of about 24,000 W at about 1.6 mTorrwith a bias of about 300 W. Under such conditions a 150 Å thick TaNbottom barrier layer 306 b can be formed in about 120 s (seconds). Theinventors point out that the aforementioned parameters and specificapplications are given merely as an example that illustrates much widerprinciples of operation.

Referring to FIG. 3(c), the bottom portion of the non-uniform barrierlayer 306 is removed to expose the underlying metal layer 304 b. Aspreviously disclosed, the preferred approach for removing the bottombarrier layer 306 b is by anisotropically (directionally) etching thesubstrate. As explained above, anisotropic etching can be achieved in anumber of ways known to those of ordinary skill in the art. For example,plasma etching, reactive ion etching (RIE), or ion milling can be used.The same etchants and process operations as disclosed hereinabove can beused.

The substrate is exposed to a directional flow of etchants 307 until thebottom barrier layer 306 b is removed. As before, the intended effect ofthe anisotropic etching is to remove the bottom barrier layer 306 b,exposing a portion 304 b of the underlying conducting layer 204. Thisexposed conducting surface 304 b is now in readiness for copperinterconnect formation.

Referring to FIG. 3(d) a copper-containing material is formed in theopening to create a conductive plug 310. As explained above, theprocesses for forming such copper-containing plugs 310 are well known.For example, a thin seed layer of copper material can be formed insidethe opening and then the seed layer is treated to achieve the bulkdeposition off copper materials to form the plug 310 in the opening.

FIGS. 4(a)-4(d) illustrate another approach for anisotropically etchingaway of a bottom portion of a barrier layer and the subsequent formationof an improved copper interconnect. Referring to FIG. 4(a), a substrateis formed similar to those previously described (e.g., as in FIGS. 2(a)or 3(b)). The substrate 400 includes a conducting layer 204 formedthereon. As before, the conducting layers 204 are typically formed ofcopper-containing materials as described hereinabove. Also as above, aninsulating layer 203 is formed on the substrate surface. Also as above,openings 408 are formed in the insulating layer 203 using methodologieswell known to those having ordinary skill in the art. The openingsexpose a portion 404 b of the underlying conducting layer 204. Also aspreviously disclosed, a barrier layer 406 is formed on the substrate.Processes for forming such layers are as described as in FIGS. 2(a)-2(d)or FIGS. 3(a)-3(d) can be used. Also, as is known to persons havingordinary skill in the art, many other methods of forming such barrierlayers can be used. A non-uniform barrier layer 406 is preferred (butnot required) due to the ability to form very thin bottom barrierlayers.

Referring to FIG. 4(b), the barrier layer 406 of the substrate 400 isthen exposed to a flood ion beam 407 to anisotropically remove thebottom layer 406 b of the barrier layer. Such a flood ion beam can beused to sputter material off the bottom of the openings. Such amethodology can be achieved using, for example, a High Density PlasmaFlood System such as manufactured by Applied Materials, Inc. of SantaClara, Calif. For example, such a system can use an energized argon (Ar)gas to produce an Ar plasma which is directed onto the substrate. Usingion densities in the range of about 1×10¹⁶ to about 2×10²⁰ ions per m²suitable barrier layer removal can be achieved at the bottom of theopening to expose the underlying conducting layer 204. Suitable plasmaenergies are in the range of about 5 eV to about 50 eV for Ar plasma,and about 2 eV to about 50 eV for electrons.

Such a process can be used to produce a substrate similar to thatdepicted in FIG. 4(c). Such substrate can be cleaned to remove oxidesand then treated to form an interconnect structure. As explained above,the processes for forming such interconnect structures are well known.For example, a thin seed layer of copper material can be formed insidethe opening and then the seed layer is treated to achieve the bulkdeposition off copper materials to form the interconnect in the opening.This structure can be used to form vias as well as many otherstructures. Reference to FIG. 4(d) shows a copper plug 410 filling theopening to comprise an interconnect via. No barrier material is presentat the interface 412 between the interconnect plug 410 and theunderlying conducting layer 204. Such a structure has a superiorelectromigration lifetime and improved resistance to void inducedcircuit failure.

Referring to FIG. 5, a semiconductor wafer is depicted. Typically, suchwafers 501 having a multiplicity of integrated circuits (chips) 502formed thereon. Each chip has many different types of circuit structuresformed thereon. Accordingly, each chip 502 can include structures asdepicted FIGS. 2, 3, and 4 (schematically depicted here as interconnect503) as part of its structure.

FIG. 6 shows a flow diagram that depicts one embodiment of theabove-described process. The method embodiment of FIG. 6 can be used toconstruct copper interconnects that are resistant to void inducedfailure and have longer electromigration lifetimes than conventionalinterconnects. The method involves providing a substrate having suitablesubstrate (Step 601). Such a substrate includes a conductive layercomprising a copper-containing material and having an insulating layerformed thereon. The insulating layer has openings that expose portionsof the underlying conductive layer at the bottom of the openings. Abarrier layer is then formed on the substrate (Step 603). Such barrierlayers cover the insulating layer and the exposed portion of theconductive layer. Methods of forming such barrier layers are welldescribed herein. Such layers include, but are not limited to, thenon-uniform barrier layers described herein. The barrier layer at thebottom of the openings is then removed to expose the underlyingconductive layer (Step 605). Such barrier layer removal is typicallyaccomplished using anisotropic material removal processes (e.g., etchtechniques) but is not limited to such. Conductive plugs are formed inthe opening such that the bottom of the plug is in contact with theexposed conductive layer (Step 607). The present invention furthercovers semiconductor devices formed by the above method.

The present invention has been particularly shown and described withrespect to certain preferred embodiments and specific features thereof.However, it should be noted that the above-described embodiments areintended to describe the principles of the invention, not limit itsscope. Therefore, as is readily apparent to those of ordinary skill inthe art, various changes and modifications in form and detail may bemade without departing from the spirit and scope of the invention as setforth in the appended claims. Other embodiments and variations to thedepicted embodiments will be apparent to those skilled in the art andmay be made without departing from the spirit and scope of the inventionas defined in the following claims. In particular, it is contemplated bythe inventors that barrier layers in accordance with the principles ofthe present invention can be practiced with a number of differentmaterials and formed by a wide variety of methods. Further, reference inthe claims to an element in the singular is not intended to mean “oneand only one” unless explicitly stated, but rather, “one or more”.Furthermore, the embodiments illustratively disclosed herein can bepracticed without any element which is not specifically disclosedherein.

1-18. (Canceled).
 19. A copper interconnect structure having increasedresistance to electromigration, the interconnect comprising: asemiconductor substrate; a conductive layer formed of copper-containingmaterial formed on the substrate; an insulating layer formed on the atleast one conductive layer, the insulating layer having an opening thatexposes a portion of the underlying conductive layer at the bottom ofthe opening the opening also including sidewalls; a barrier layer formedon the sidewall of the opening, the barrier layer being formed of amaterial that is resistant to copper diffusion into the insulatinglayer; and a conductive plug comprised of copper-containing material isformed in the opening such that the bottom of the plug is in contactwith the underlying exposed conductive layer.
 20. The copperinterconnect of claim 19 wherein the insulating layer is formed of low-Kdielectric.
 21. The barrier layer of claim 19 wherein the metal barrierlayer is formed of material including at least one of tantalum, tantalumnitride, titanium, titanium nitride, palladium, chromium, tantalum,magnesium, and molybdenum.
 22. A semiconductor integrated circuitincorporating the structure of claim 19.